================================ Instruction set for the Mini ALU [TOC] ================================ This section is about encoding and decoding instructions for our Mini ALU. Relevant for encoding/decoding an instruction is the instruction set which in particularly specifies what operations are supported and describes the format of an instruction. Video tutorial ============== ---- VIDEO ------------------------------ https://www.youtube.com/embed/bNXpplKzZTc ----------------------------------------- Supplements for instruction set and the introduced notations ============================================================ All instructions are 8-bit patterns and have a simple format. The format can be described by grouping the bits by pairs and denoting them, from left to right, as `Op`, `X`, `Y` and `Z`. For example ---- LATEX --------------------------------------------------------------------- \text{10011011} \leadsto \text{10 01 10 11} \leadsto \text{Op} = \text{10}, \text{X} = \text{01}, \text{Y} = \text{10}, \text{Z} = \text{11}. -------------------------------------------------------------------------------- The bit pattern `Op` is the __opcode__ of the instruction. It specifies the type of instruction. Because the opcode is a 2-bit pattern we have (only) 4 types of instructions, and the remaining bits are used as operands. The instruction set of the ALU can be described as follows: ---- LATEX --------------------------------------------------------------------- \begin{array}{ll} \text{Op} & \text{Effect} \\ 00 & \bigl(u(\text{%}00) + u(\text{XY})\bigr) \bmod 2^8 \to u(\text{%}Z) \\ 01 & \bigl(u(\text{%}Z)\cdot 2^4 + u(\text{XY})\bigr) \bmod 2^8 \to u(\text{%}Z) \\ 10 & \bigl(u(\text{%}Y) + u(\text{%}X)\bigr) \bmod 2^8 \to u(\text{%}Z) \\ 11 & \bigl(u(\text{%}Y) - u(\text{%}X)\bigr) \bmod 2^8 \to u(\text{%}Z) \\ \end{array} -------------------------------------------------------------------------------- In this description the following conventions and formal notations are used: - With `XY` the concatenated bit pattern of `X` and `Y` is denoted. For example, if `X = 01` and `Y = 10` then `XY` denotes `0110`. - A register with id `X` is addressed by using the `%`. Hence, `%00` denotes register with id `00`, `%01` denotes register with id `01`, etc. - Whit the notation $u(\dots)$ the interpretation of the bit pattern as _unsigned integer_ is expressed. This basically an abbreviation for the positional notation with base $2$: ---- LATEX ------------------------------------------------------------------- u(\text{"bit pattern"}) := (\text{"bit pattern"})_2 ------------------------------------------------------------------------------ so for example ---- LATEX ------------------------------------------------------------------- u(1011) := (1011)_2 := 8 + 2+ 1. ------------------------------------------------------------------------------ The motivation to introduce another notation will become clear when we introduce the notation $s(\dots)$ for the interpretation as _signed integer_. - For a given integer $n$ we describe with $n \to u(\text{%}Z)$ how a _destination register_ gets changed by an instruction. For $n \in \{0,\dots,2^8-1\}$ there is an unique 8-bit pattern $N$ such that $n = u(N)$ so this denotes that $\text{%}Z$ gets overwritten by $N$. This method of describing an instruction set was developed by Donald Knuth (see __Volume 1 Fascicle 1 of TAOCP__ were he describes his __MMIX__). It has the advantage that you can describe the effect of an instruction without the need to describe how the instruction is implemented. The price for this elegance requires some idealised hardware design (that is why you realize it by a virtual machine and not actual hardware) but it is perfect for teaching. And most important, it is giving you the essential idea. If you want to see a description of an instruction set from the industrial world have a look at the ARM instruction set (e.g. in__Armv8-M Architecture Reference Manual__) or the Intel 64 instruction set (e.g. __Intel® 64 and IA-32 Architectures Software Developer’s Manual__). Both look scary at first, but you will see that having the big picture makes them readable! Description of the register bank (using the notations) ====================================================== For the register bank we can now express with $\text{out0} \leadsto \text{%}\text{sel_out0}$ that the output `out0` is connected to the register with id `sel_out0`. So in total the register bankk can be described as ---- LATEX --------------------------------------------------------------------- \text{out0} \leadsto \text{%}\text{sel_out0}, \; \text{out1} \leadsto \text{%}\text{sel_out1}, \; \text{in} \leadsto \text{%}\text{sel_in}, \; -------------------------------------------------------------------------------- and ---- LATEX --------------------------------------------------------------------- \text{%}\text{sel_in} = \text{in},\;\text{if}\;\text{clock}=1. -------------------------------------------------------------------------------- In particular this makes it easy to describe the role of the register bank for implementing the instruction set. For example, implementing the operation $\bigl(u(\text{%}Y) + u(\text{%}X)\bigr) \bmod 2^8 \to u(\text{%}Z)$ requires ---- LATEX --------------------------------------------------------------------- \text{out0} \leadsto \text{%}\text{Y}, \; \text{out1} \leadsto \text{%}\text{X}, \; \text{in} \leadsto \text{%}\text{Z} -------------------------------------------------------------------------------- so that we get the needed source and destination registers for the adder. How this prepares you for upcoming sessions =========================================== The format used for the ALU is very similar to the format used by the 32-bit instruction of the __MMIX__ or the __ULM__. :links: opcode -> https://en.wikipedia.org/wiki/Opcode Volume 1 Fascicle 1 of TAOCP -> http://mmix.cs.hm.edu/doc/fasc1.pdf MMIX -> http://mmix.cs.hm.edu ULM -> http://www.mathematik.uni-ulm.de/~lehn/ulm/ulm.pdf Armv8-M Architecture Reference Manual -> https://static.docs.arm.com/ddi0553/bk/DDI0553B_k_armv8m_arm.pdf?_ga=2.219979161.1832383504.1587987227-785972965.1587987227 Intel® 64 and IA-32 Architectures Software Developer’s Manual -> https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf :navigate: up -> doc:index next -> doc:session03/page04 back -> doc:session03/page02