========================================= ULM Generator (Part 3): Jump Instructions [TOC] ========================================= ---- VIDEO ------------------------------ https://www.youtube.com/embed/x1kaem5VZEA ----------------------------------------- Material: Instruction Set and `cat` Program =========================================== Here the final instruction set that was created: ---- CODE (file=session08/cat/isa.txt, fold) ----------------------------------- RRR (OP u 8) (X u 8) (Y u 8) (Z u 8) J26 (OP u 8) (XYZ j 24) 0x01 RRR ulm_halt(ulm_regVal(X)); 0x02 RRR ulm_setReg(ulm_readChar() & 0xFF, X); 0x03 RRR ulm_printChar(ulm_regVal(X) & 0xFF); 0x04 J26 ulm_unconditionalRelJump(XYZ); 0x05 RRR ulm_sub64(X, ulm_regVal(Y), Z); 0x06 J26 ulm_conditionalRelJump(ulm_statusReg[ULM_ZF] == 0, XYZ); 0x07 J26 ulm_conditionalRelJump(ulm_statusReg[ULM_ZF] == 1, XYZ); -------------------------------------------------------------------------------- And here the `cat` program: ---- CODE (file=session08/cat/cat, fold) --------------------------------------- 02 01 00 00 05 FF 01 00 07 00 00 03 03 01 00 00 04 FF FF FC 01 00 00 00 -------------------------------------------------------------------------------- Related Topic: Instruction Pipelining ===================================== In the video you saw that the ULM is executing instructions in 4 _pipeline stages_ (there just called stages A to D). This reflects how commonly used hardware executes instructions in the micro architecture. However, usually more than 4 stages will be involved. In the video these stages where used to explain the sequential execution of programs and how _jump instructions_ (these are also called _branch instructions_) are realized. In practise these pipeline stages are one leverage to optimize the micro architecture without affecting the ISA. That means programs written for the ISA (potentially) will just run faster but you do not have to rewrite them. This optimization is called __Instruction Pipelining__. And we should discuss that in class. You will see that you now have the necessary basic knowledge - to understand how this optimization can speed up the program execution - why in certain cases this has no or a limited effect - what kind of code actually can take most advantage of it The concept of instruction pipelining is also explained by __Jon Rubinstein__ in his 5 minute talk about the __Megahertz myth__. Were in particular points out what other factors are essential for optimizing the architecture: ---- VIDEO ------------------------------ https://www.youtube.com/embed/TJN5GfZuVog ----------------------------------------- :links: Instruction Pipelining -> https://en.wikipedia.org/wiki/Instruction_pipelining Jon Rubinstein -> https://en.wikipedia.org/wiki/Jon_Rubinstein Megahertz myth -> https://en.wikipedia.org/wiki/Megahertz_myth