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Crash Course in SystemVerilog: Sequential Logic [TOC]
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In the lecture, we've seen that circuits with flip-flops require consideration
of clock signal edges in their mathematical descriptions. This can be achieved
by describing a sequence of logical states. For example, with the equations
(initial value of ) and  (value of  after a rising edge), the following circuit
with a flip-flop and an inverter can be described:

---- IMAGE (width=600) -----------
session06/s06_2.png
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In SystemVerilog, this can be described as follows:

---- CODE(file=session06/page03/Example3.sv, type=abc, linenumbers) ------------
module Example3 (
    input logic clock,
    output logic Q
);

    initial begin
        Q = 0;
    end

    always_ff @ (posedge clock) begin
        Q <= ~Q;
    end

endmodule
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The initial value is set in the "initial" block, and how the state of `Q`
changes after a rising edge is described in the `always_ff` block (`ff` stands
for Flip-Flop).

Of course, SystemVerilog allows expressing that a circuit consists of both
logic gates and flip-flops, and accordingly, it can be described with both
combinatorial and sequential logic. For example, this circuit

---- IMAGE (width=600) -----------
session06/s06_3.png
----------------------------------

can be described by the following SystemVerilog code:

---- CODE(file=session06/page03/Example4.sv, type=abc, linenumbers) ------------
module test (
    input logic a,
    input logic clock,
    output logic Q
);

    logic nextQ;

    initial begin
        Q = 0;
    end

    always_comb begin
        nextQ = ~Q | a;
    end

    always_ff @ (posedge clock) begin
        Q <= nextQ;
    end

endmodule
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