Puzzle Task

Given the following SystemVerilog code:

session06/page03/Puzzle.sv 
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module Puzzle (
    input logic clock,
    output logic Q1,
    output logic Q2
);

    initial begin
        Q1 = 0;
        Q2 = 0;
    end

    always_comb begin
        nextQ1 = ~Q1 | Q2;
        nextQ2 = ~(Q1 & Q2);
    end

    always_ff @ (posedge clock) begin
        Q1 <= nextQ1;
        Q2 <= nextQ2;
    end

endmodule

Part 1: Realization in CircuitVerse

Create a circuit in CircuitVerse that corresponds to this description. Note that the circuit is not uniquely determined by the SystemVerilog code; there are multiple possible realizations.

Part 2: Mathematical Description

Mathematically describe this module using equations for \(Q_1^{(n)}\) and \(Q_2^{(n)}\).

Part 3: Proof of the Impossibility of Certain States

Show that regardless of how the initial values of \(Q_1^{(0)}\) and \(Q_2^{(0)}\) are chosen, the states \(Q_1^{(n)}=0\) and \(Q_2^{(n)}=0\) for \(n > 0\) can never be reached.